1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device having step portions on the surface of the semiconductor substrate. This invention also relates to a method of manufacturing such a device.
2. Description of the Prior Art
In the process of manufacturing semiconductor devices such as semiconductor laser diodes, step portions such as mesa patterns or concave portions formed on a semiconductor substrate must be buried by growing semiconductor crystal layers. It is generally known that a liquid phase epitaxial growth method can effectively grow semiconductor crystal layers so as to bury such step portions. As a result, the surface of the semiconductor substrate becomes flat. However, when this crystal growth is performed by a vapor phase epitaxial growing method, a problem will arise.
Specifically, in the case when the thickness of steps are less than 1 .mu.m, there is substantially no problem. When the thickness of such steps are greater than 1 .mu.m, however, mesa patterns cannot be satisfactorily buried. This is because some projections grow from the sides of steps. These projections prevent the crystal growth (as disclosed in the transactions of Electronics and Communications conference, 865, spring 1987; and Applied Physics conference, 30 p, ZH-8, spring 1987).
As described above, mesa patterns are formed on a semiconductor substrate as steps. Thereafter, semiconductor crystal layers are grown on such steps. In the conventional process, the substrate surface is in a plane of {100}-orientation. One of mesa patterns is formed in a &lt;110&gt;-direction. The direction of such a mesa pattern is inevitably determined in the &lt;110&gt;-direction. The reason is that when manufacturing a semiconductor laser diode, the longitudinal direction of the mesa pattern is determined so as to intersect perpendicularly to a (110)-plane. The (100)-plane is a resonator side formed by a crystal cleavage. When the longitudinal direction of the mesa pattern is formed in the &lt;110&gt; direction, a plane of {111}-orientation appears on the side of the mesa pattern. Thus, a projection grows in a direction parallel to a {111}-plane.
Therefore, in the conventional method, to avoid the above-described problem, the process of forming a mesa pattern and burying the same is divided into small processes. Specifically, the step of mesa pattern is limited to 1 .mu.m or less at a time. However, this method requires a large number of times of crystal growth. Thus, the process becomes cumbersome and complicated. Moreover, when designing the devices, various restrictions are inevitably imposed on the configuration of the devices.
As described above, when mesa patterns of 1 .mu.m or more in thickness are formed on a substrate of a {100}-plane in the &lt;110&gt;-direction, a vapor phase epitaxial growing method cannot bury the mesa patterns satisfactorily to allow the substrate surface to become flat. Further, the process of manufacturing semiconductor devices such as semiconductor laser diodes becomes cumbersome and complicated because of the above-described reasons. Moreover, the degree of freedom in the design of such devices is lowered.
On the other hand, such semiconductor devices have received practical applications that utilizes phenomena such as light emission, light reception, and light amplification. These are achieved simply by applying bias voltages to a p-n junction of each semiconductor device. Such semiconductor devices are strongly required to achieve higher performance along with an increase in the processing speed of information. Particularly, the requirements for high speed response characteristics are significant. Thus, the research and development on these characteristics have been actively carried out in recent years.
In order to realize high speed response characteristics, semiconductor elements are required to be integrated on one single plane. This is generally called a planar structure. Further, it is necessary to reduce parasitic capacitance by using a high resistance semiconductor substrate. The semiconductor laser diodes of the conventional planar structure have already been disclosed in Japanese Patent Publications No. 55-111188 and No. 62-112390. The optical sensors have also been disclosed in the transactions of "Opto Electronics Conference '86, P6". Hereinafter, the conventional technology on these will be briefly described with reference to FIGS. 10 and 11.
In FIG. 10, reference numeral 71 represents a semi-insulating substrate,, and 72 represents a n-type semiconductor that forms steps together with the substrate 71. Reference numerals 73 through 76 represent p-type semiconductor layers formed on the step portions, and 77 and 78 represent electrodes. This structure has the following problems. Because of steps formed on the surface of elements, it is difficult to perform microscopic processing in terms of integration. Since the electrodes are formed on the respective semiconductor layers, parasitic capacitance thereabout is large. If bonding pads or electrodes are formed on the semi-insulating substrate to reduce the parasitic capacitance thereabout, the number of step portions inevitably increases.
In FIG. 11, 81 represents a high-resistance semiconductor substrate, and 82 through 84 represent n-type semiconductor layers formed in the concave portion of the substrate 81. Reference numeral 85 represents a p-type diffusion layer formed selectively on the layer 84, and 86 represents an insulating film, then 87 and 88 represent electrodes. This structure has the following problems. In order to form gradual inclinations in the concave portion of the substrate 81, a high technical skill in manufacturing is necessary. For instance, Ar ion beam etching or two-layer photoresist processing is required. Moreover, the contact areas of the electrodes 87 and 88 with respect to semiconductor layers 82 through 84 are small. Thus, the contact resistance therebetween is high. Further, parasitic capacitance exists between the electrode 88 and the semiconductor layers 82 through 84 which are present on opposite sides of the insulating film 86.
As described above, in a semiconductor device of a planar structure, there have been the following problems. The steps formed on the surface of elements are disadvantageous to integration. The parasitic capacitance between the elements cannot be sufficiently reduced. The contact resistance between the electrodes and the semiconductor layer is high. Further, the process of manufacturing the devices becomes cumbersome and complicated.